The present invention generally relates to the isolation of semiconductor devices in integrated circuits by using isolation structures, thus enabling increase of the packing density and isolation.
More specifically, the invention relates to a method for fabrication of a semiconductor structure comprising a shallow isolation region and a deep trench isolation region, to the semiconductor structure itself, and to an integrated circuit comprising such a semiconductor structure.
All non-trivial integrated electronics involves connecting isolated devices through specific electrical connection paths. The device isolation scheme is therefore one of the critical parts when fabricating integrated circuits. Many different schemes have been developed during the years. Parameters like minimum isolation spacing, surface planarity, defect density, process complexity and electrical properties, i.e. DC and high frequency properties, influence the choice of a scheme for the particular application and process technology. Mesa isolation, junction isolation and LOCOS (local oxidation of silicon) isolation are common techniques in use, see e.g. Chapter 2 in S. Wolf, xe2x80x9cSilicon Processing for the VLSI ERA, Volume 2xe2x80x94Process integrationxe2x80x9d, Lattice Press, Sunset Beach, 1990.
As feature sizes in modern, high-complexity integrated circuits (ULSI, ultra large scale integration) decreases, there is a need to reduce shortcomings, such as packing density, leakage currents and latch-up between devices, associated with older isolation technologies. Shallow and deep trench isolations have therefore become very popular. Although demanding on the etching and refilling process steps, they offer vast improvement in decreased area needed for the isolation between circuit elements and e.g. storage capacitors in DRAM memory technologies.
The trenches are formed by removing silicon by dry etching and filling them with suitable dielectric or conductive materials. Shallow trench isolation (STI), which is used to replace LOCOS isolation, usually has a depth of a few tenths of a micron and is used for isolation between device elements. Shallow trench isolation is closer described in e.g. xe2x80x9cChoices and Challenges for Shallow Trench Isolationxe2x80x9d, Semiconductor International, April 1999, p. 69. Deep trenches, usually with a depth larger than a couple of microns, are mainly used to isolate different devices and device groups (wells) in CMOS/BiCMOS technology, to form vertical capacitors and to form high-conductive contacts to the substrate, see C. Y. Chang and S. M. Sze (Eds); xe2x80x9cULSI Technologyxe2x80x9d, McGraw-Hill, New York, 1996, pp. 355-357 and WO 97/35344 (inventors: Jarstad and Norstrom). The trenches are filled with oxide, polysilicon or other materials, and the surface is pianarized, either by dry etching of by chemical mechanical polishing (CMP).
In U.S. Pat. No. 4,994,406 issued to Vasquez and Zoebel is described a method to form shallow and self-aligned deep isolation trenches on an integrated circuit. Although the deep trench are being self-aligned to the edge of the device areas, the structure uses a polysilicon nitride stack to form device isolation using LOCOS, with large lateral encroachment, high temperature budget, and a non-planar surface as a result.
U.S. Pat. No. 5,691,232 issued to Bashir discloses a method to form shallow and deep trench isolation by combining the formation of the two. First, a shallow trench is formed using a first mask, and then a deep trench is formed using a second mask. The whole structure is filled with oxide and planarized. Since the mask for the deep trench must be aligned against the mask for the shallow trench, less packing density is achieved and/or leakage current problems will occur when the structure is scaled. Also, filling of narrow deep trenches usually requires the use of polysilicon and back etching, not included in this description.
In U.S. Pat. No. 5,895,253 issued to Akram is described a method to form a deep trench within a shallow trench and how to fill it with an insulator. The deep trench is self-aligned within the shallow trench. This is made with only one mask step. After forming the trench, it is filled in a common way. Although the patent teaches how to place a deep trench self-aligned within the shallow trench, the method uses only one mask step, and it will not be possible to use shallow trenches without any deep trench. The width of the deep trench is set by the width of the shallow trench opening and spacer widths. If different shallow trench openings are used, the etching and filling of the deep trenches will become difficult or even impossible.
It is consequently an object of the present invention to provide a method in the fabrication of an integrated circuit, particularly an integrated circuit for radio frequency applications, for forming shallow and deep trenches for isolation of semiconductor devices comprised in said circuit, while overcoming at least some of the problems associated with the prior art.
It is a further object of the invention to provide a fabrication method that permits deep trenches to be placed inside shallow trench regions, with adjustable distance from the edge of the shallow trench to the deep trench, still allowing the formation of shallow trench areas without any deep trenches inside.
It is yet a further object of the invention to provide such a method having enhanced scalability characteristics enabling an increased packing density.
It is still a further object of the invention to provide such a method having increased integration flexibility and which is compatible with several technologies.
These objects among others are, according to one aspect of the invention, fulfilled by a method comprising the following steps:
providing a semiconductor substrate;
optionally forming a first dielectric layer on said substrate;
forming at least one shallow trench in said first dielectric layer or in said substrate by using a first mask formed on said first dielectric layer, said shallow trench extending into said substrate;
forming a second dielectric layer of a predetermined thickness, 2x, on the structure obtained subsequent to the step of forming the at least one shallow trench;
forming at least one opening in said second dielectric layer by using a second mask formed on said second dielectric layer and with an edge of said second mask aligned to an edge of said shallow trench with a maximum misalignment of half the predetermined thickness of said second dielectric layer, i.e. +/xe2x88x92 x, said opening extending within the shallow trench to the bottom thereof, whereby a spacer of a width equal to the predetermined thickness, 2x, is formed in said shallow trench and along said edge thereof; and
forming a deep trench in said opening by using said second dielectric layer as a hard mask, said deep trench extending further into said substrate and being self-aligned to said shallow trench.
Furthermore it is an object of the present invention to provide a semiconductor structure resulting from above said fabrication method.
According to a second aspect of the present invention there is thus provided a semiconductor structure comprising a semiconductor substrate; at least one shallow trench extending vertically into said substrate; a deep trench laterally within said shallow trench, said deep trench extending vertically further into said substrate, wherein said deep trench is self-aligned to said shallow trench with a controlled lateral distance between an edge of the shallow trench and an edge of the deep trench, and the lateral extensions of the shallow and deep trenches, respectively, are independently chosen.
An advantage of the present invention is that the distance between the deep and shallow trench edges is fixed and determined by the thickness of the deposited second dielectric layer, thus easily controllable.
Another advantage of the invention is that the distance between the deep and shallow trench edges is minimized in order to obtain an increased packing density of the integrated circuit, still providing a step between them in order to prevent stress arising from deep trench processing to interfere with active areas.
Further advantages and characteristics of the present invention will be disclosed in the following detailed description of embodiments.